The present invention relates to a phase detector and in particular to phase detector apparatus for detecting a difference in phase between two input signals.
Phase detectors are used in many systems such as phase lock loops, delay lock loops and clock and data recovery circuits. Typically, a delay lock loop circuit may consist of a phase detector having an output connected to a low pass filter which in turn has an output connected to a variable delay circuit. A clock input signal is applied as one input signal to the phase detector and as an input signal to the input of the variable delay circuit which in turn applies a delayed input signal to another input of the phase detector. The phase detector measures the phase of the one input signal versus the delayed input signal and produces an output that represents the phase shift between the two input signals applied to the phase detector. The low pass filter averages the output of the phase detector output and produces an output to adjust the variable delay circuit. This negative feedback signal loop settles into a steady state value that ideally achieves zero phase error at the input of the phase detector. Depending on the design, the lock can be chosen to be zero, ∘, 2∘, etc. With conventional phase detectors, any asymmetry in the phase detector can cause the delay lock loop to create a static phase error at the input of the phase detector resulting in an error in the delay circuit setting. Thus, the design of the phase detector is an extremely critical circuit in the delay lock loop as well as other phase measurement circuits.
Phase detectors may either be a linear or nonlinear detector. The linear detector produces an output that is ideally proportional to the phase difference between the two input signals to the phase detector. In contrast, a nonlinear or digital phase detector, sometimes called a xe2x80x9cbang bangxe2x80x9d phase detector, produces an output that simply indicates whether one input is leading the other input. Linear phase detectors are generally used with a delay lock loop having an analog loop filter whereas a nonlinear or digital phase detector can be used with either a digital or analog loop filter.
The simplest type of nonlinear or digital phase detector is a well known master slave D flip flop logic circuit having one input signal, hereinafter referred to as an xe2x80x9crxe2x80x9d signal, connected to the clock input of the flip flop and the other input signal, hereinafter referred to as a xe2x80x9cvxe2x80x9d signal, connected to the D input. If the rising edge of the xe2x80x9crxe2x80x9d input signal leads the rising edge of the xe2x80x9cvxe2x80x9d input signal, the phase detector flip flop generates a xe2x80x9czeroxe2x80x9d output signal indicating that the xe2x80x9cvxe2x80x9d input signal should be advanced. If the rising edge of the xe2x80x9crxe2x80x9dinput signal lags the rising edge of the xe2x80x9cvxe2x80x9d input signal, the phase detector flip flop generates a xe2x80x9conexe2x80x9d output signal indicating that the xe2x80x9cvxe2x80x9d input signal should be retarded. Such a digital phase detector works well if the D flip flop has zero setup time. Assuming a finite setup time, the D flip flop phase detector operating in a feedback loop will create a static phase error equal to the flip flop setup time. In low speed delay lock loop applications such a static phase error may be acceptable, however, in extremely high speed or precision applications a static phase error equal to the setup time is unacceptable.
The static phase error, even under ideal circuit conditions will occur because the D flip flop is asymmetrical with respect to the D and clock inputs. A precise digital phase detector thus requires complete symmetry in the two inputs of the digital phase detector. A prior art solution was to design a symmetrical multi-gate flip flop circuit using a multiplicity of logic gates. A problem arises in this design in that, in addition to the power dissipation of the circuit topology, the frequency of the input signals is limited by the large number of gate delays incurred for latching the decision as well as propagating the latched decision to the output.
It is an object of the invention to provide a high speed and low power phase detector with a master stage having imbalanced latching devices with intentional input-referred offset for determining which one of a pair of input signals is leading the other and which has a slave stage connected to the imbalanced latching devices and which is transparent when ones of the imbalanced latching devices are activated and which is latched and held when the imbalanced latching devices are reset for the next measurement.
It is also an object of the invention to provide a phase detector having a pair of imbalanced latching devices each having one element connected to a first master load component and each having another element connected to a second master load component wherein one of the elements are sized larger by a range of two or more times than other one of the elements for creating an input referred offset.
It is also an object of the invention to provide a phase detector having a pair of master conducting elements each connected in series with one of a pair of imbalanced latching devices wherein each master conducting element is responsive to input signals for enabling one of the imbalanced latching devices.
It is also an object of the invention to provide a phase detector having a master bias control element connected in series with a pair of master conducting elements each connected in series with an imbalanced latching device and which is enabled by a bias control signal for enabling the master conducting elements to respond to selected values of the input signals to control operation of the imbalanced latching devices.
It is also an object of the invention to provide a phase detector having a slave stage with a pair of slave load components and a first pair of slave conducting elements each in series with one of the slave load components and each having an input connected to master load components to respond to latched input signals developed by imbalanced latching devices across the master load components.
It is also an object of the invention to provide a phase detector having a slave stage with a second pair of slave conducting elements connected in a parallel configuration in series with a first pair of slave conducting elements connected to slave load components and responsive to ones of input signals for enabling operation of ones of the first pair of slave conducting elements in response to signals latched on a pair of imbalanced load devices.
In a preferred embodiment of the invention, a phase detector embodying principles of the invention includes a master stage or circuit having imbalanced latching devices with intentional input-referred offset for determining which one of a pair of input signals is leading the other and a slave stage or circuit connected to the imbalanced latching devices which is transparent when the latching devices are set to an activate state and which are latched and held when the latching devices are set to an inactivate state.
Also in accordance with an embodiment of the invention a phase detector has a pair of master imbalanced latching devices each having a pair of elements of which one latching element is sized larger than the second latching element for creating an input referred offset and are connected in a feedback configuration with pro-designed imbalance in opposite directions. A pair of master conducting elements is each connected in series with one of the pair of the master imbalanced latching devices and each is responsive to one of a pair of input signals for enabling one of the imbalanced latching devices. In addition, a master bias control element is connected in series with the pair of master conducting elements and is enabled by a bias control signal for enabling the master conducting elements to respond to selected values of the input signals. Master symmetrical circuit apparatus is connected in parallel with a master load and the pair of imbalanced latching devices and the master conducting elements and is enabled by complementary ones of the input signals for maintaining a current flow in the bias control signal element. The phase detector has a slave stage with a first pair of slave conducting elements each having an input connected to the master imbalanced latching devices to respond to latched input signals developed by the imbalanced latching devices. A second pair of slave conducting elements connected in a parallel configuration in series with the first pair of slave conducting elements and slave load components is responsive to ones of enabling input signals. In addition, a slave bias control element connected in series with the slave load components and the first and second pair of slave conducting elements responds to the bias control signal for enabling the first and second pair of slave conducting elements to respond to selected values of the input and latched input signals. A slave latching device connected across the slave load devices, latches and holds signals developed across the slave load means. Two pairs of corresponding slave circuit elements connected in a symmetrical configuration in a series relationship to the slave latching device and in parallel across the combination of the first and second pair of slave conducting elements with each pair of corresponding slave circuit elements connected to respond to complementary input signals to compensate for variations occurring in the complementary input signals controlling operation of the slave bias control element.
Also in accordance with another embodiment of the invention, a phase detector has a pair of back to back master inverters forming a latch connected in series with a pair of parallel master conducting elements each responsive to one of input signals for enabling the master latch. Slave apparatus having a combination of a parallel pair of slave connecting elements connected in series with a slave inverter to one of the master inverters is enabled by either one of the input signals for coupling an output of the one back to back inverter to the slave inverter. In addition, load balance or complementary output apparatus comprising a combination of a parallel pair of load balance connecting elements connected in series with a load balance inverter to the other master inverter is enabled by either one of the input signals for coupling an output of the other master latch inverter to the load balance inverter to act in combination with the slave apparatus to balance the digital phase detector. The phase detector also has a first pair of two series connected master conducting elements with two of the master conducting elements of one of the first pair connected between a supply voltage and the input of the slave apparatus and with two of the master conducting elements of the other first pair connected between the supply voltage and the input to the load balance apparatus and with each pair of master conducting elements responsive to both of the input signals being a logical zero for applying the supply voltage to the inputs of the slave and load balance apparatus. A second pair of two series connected master conducting elements is also provided with each one of the two series connected master conducting elements connected between ground and the input to the slave and load balance apparatus, respectively. One master conducting element of each second pair is sized in a range between two, three or more times larger than corresponding elements of the master inverters and with the other conducting element of each second pair enabled by ones of the input signals for providing intentional input-referred offset for the master inverter latch.
Also in accordance with an embodiment of the invention, a phase detector latch has a load and a pair of imbalanced conducting elements each connected to the load and each connected in a direct connected feedback configuration with pre-designed imbalance in opposite directions wherein a first one of the imbalanced conducting elements is sized in a range of two, three or more times larger than the size of the second imbalanced latching element. A master conducting element connected in series with the load and the direct connected imbalanced conducting elements is responsive to an input signal for latching the larger sized imbalanced conducting element to a predefined state.